'Finite State Machine Synthesis' - Computer Science and Engineering (IIT Guwahati) Video Lectures by Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

Watch Design Verification and Test of Digital VLSI Circuits ('Computer Science and Engineering' course from IIT Guwahati) Video Lectures by Dr. Santosh Biswas, Prof. Jatindra Kumar Deka.

Course: Design Verification and Test of Digital VLSI Circuits

Discipline: Computer Science and Engineering

Faculty: Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

Institute: IIT Guwahati

NPTEL Lecture : 'Finite State Machine Synthesis'