Design Verification and Test of Digital VLSI Circuits Video Lectures

Design Verification and Test of Digital VLSI Circuits
'Design Verification and Test of Digital VLSI Circuits' Video Lectures by Dr. Santosh Biswas, Prof. Jatindra Kumar Deka from IIT Guwahati
"Design Verification and Test of Digital VLSI Circuits" - Video Lectures
1. Introduction to Digital VLSI Design Flow
2. High Level Design Representation
3. Transformations for High Level Synthesis
4. Introduction to HLS: Scheduling, Allocation and Binding Problem
5. Scheduling Algorithms-1
6. Scheduling Algorithms-2
7. Binding and Allocation Algorithms
8. Two level Boolean Logic Synthesis-1
9. Two level Boolean Logic Synthesis-2
10. Two level Boolean Logic Synthesis-3
11. Heuristic Minimization of Two-Level Circuits
12. Finite State Machine Synthesis
13. Multilevel Implementation
14. Introduction to formal methods for design verification
15. Temporal Logic: Introduction and Basic Operators
16. Syntax and Semantics of CTL
17. Syntax and Semantics of CTL – Continued
18. Equivalence between CTL Formulas
19. Introduction to Model Checking
20. Model Checking Algorithms I
21. Model Checking Algorithms II
22. Model Checking with Fairness
23. Binary Decision Diagram: Introduction and construction
24. Ordered Binary Decision Diagram
25. Operation on Ordered Binary Decision Diagram
26. Ordered Binary Decision Diagram for State Transition Systems
27. Symbolic Model Checking
28. Introduction to Digital VLSI Testing
29. Functional and Structural Testing
30. Fault Equivalence
31. Fault Simulation-1
32. Fault Simulation-2
33. Fault Simulation-3
34. Testability Measures (SCOAP)
35. Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras
36. D-Algorithm-1
37. D-Algorithm-2
38. ATPG for Synchronous Sequential Circuits
39. Scan Chain based Sequential Circuit Testing-1
40. Scan Chain based Sequential Circuit Testing-2
41. Built in Self Test-1
42. Built in Self Test-2
43. Memory Testing-1
44. Memory Testing-2
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